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    lcW                     @   s   d Z ddlZddlmZmZmZmZmZmZ ddl	m
Z
mZmZmZmZmZmZmZmZ g dZG dd deZG dd	 d	eZG d
d deZdS )z
    pygments.lexers.hdl
    ~~~~~~~~~~~~~~~~~~~

    Lexers for hardware descriptor languages.

    :copyright: Copyright 2006-2022 by the Pygments team, see AUTHORS.
    :license: BSD, see LICENSE for details.
    N)
RegexLexerbygroupsincludeusingthiswords)	TextCommentOperatorKeywordNameStringNumberPunctuation
Whitespace)VerilogLexerSystemVerilogLexer	VhdlLexerc                   @   s  e Zd ZdZdZddgZdgZdgZdZde	j
dfd	efd
eejefde	jfde	jfdefdedfdejfdejfdejfdejfdejfdejfdejfdefdejfdefdefdejfdeeejefdeeejedfedd d!efed"d#d d$e	j
fed%d&d d$ej fed'd d!ej!fd(ej"fd)efd*efgd+ed,fd-ejfd.efd
eejefd/efgd0e	j
fd1e	jfd2e	jd,fd3e	j
fd4e	j
fd5ed,fgd6ejd,fgd7Z#d8d9 Z$d:S );r   zZ
    For verilog source code with preprocessor directives.

    .. versionadded:: 1.4
    verilogvz*.vztext/x-verilog(?:\s|//.*?\n|/[*].*?[*]/)+z^\s*`definemacro\s+(\\)(\n)/(\\\n)?/(\n|(.|\n)*?[^\\]\n)/(\\\n)?[*](.|\n)*?[*](\\\n)?/[{}#@]L?"string4L?'(\\.|\\[0-7]{1,3}|\\x[a-fA-F0-9]{1,2}|[^\\\'\n])'%(\d+\.\d*|\.\d+|\d+)[eE][+-]?\d+[lL]?(\d+\.\d*|\.\d+|\d+[fF])[fF]?z([0-9]+)|(\'h)[0-9a-fA-F]+z([0-9]+)|(\'b)[01]+z([0-9]+)|(\'d)[0-9]+z([0-9]+)|(\'o)[0-7]+z\'[01xz]z\d+[Ll]?[~!%^&*+=|?:<>/-][()\[\],.;\']`[a-zA-Z_]\w*^(\s*)(package)(\s+)^(\s*)(import)(\s+)import)qalwaysalways_comb	always_ffalways_latchandassign	automaticbeginbreakbufbufif0bufif1casecasexcasezcmosconstcontinuedeassigndefaultdefparamdisabledoedgeelseendendcaseendfunctionendgenerate	endmodule
endpackageendprimitive
endspecifyendtableendtaskenumeventfinalforforceforeverforkfunctiongenerategenvarhighz0highz1ifinitialinoutinputintegerjoinlarge
localparammacromodulemediummodulenandnegedgenmosnornotnotif0notif1oroutputpacked	parameterpmosposedge	primitivepull0pull1pulldownpulluprcmosrefreleaserepeatreturnrnmosrpmosrtranrtranif0rtranif1scalaredsignedsmallspecify	specparamZstrengthr   strong0strong1structtabletasktrantranif0tranif1typetypedefunsignedvarvectoredvoidwaitweak0weak1whilexnorxor\bsuffix)Z
accelerateZautoexpand_vectornetsZ
celldefineZdefault_nettyper@   elsifZendcelldefineendifZ
endprotectZendprotectedZexpand_vectornetsZifdefZifndefr   ZnoaccelerateZnoexpand_vectornetsZnoremove_gatenamesZnoremove_netnamesZnounconnected_driveZprotect	protectedZremove_gatenamesZremove_netnamesZresetallZ	timescaleZunconnected_driveZundef`)prefixr   )4bitsZ
bitstorealZbitstoshortrealZcountdriversdisplayZfcloseZfdisplayfinishfloorZfmonitorZfopenZfstrobeZfwriteZ
getpatternhistoryZincsaverZ   ZitorkeylistlogZmonitorZ
monitoroffZ	monitoronZnokeyZnologZprinttimescalerandomZreadmembZreadmemhrealtimeZ
realtobitsresetZreset_countZreset_valueZrestartZrtoisavescalescopeZshortrealtobitsZ
showscopesZshowvariablesZshowvarsZ	sreadmembZ	sreadmemhZstimestopZstrobetimeZ
timeformatwritez\$)byteshortintintlongintr[   r   bitlogicregsupply0supply1tritriandtriortri0tri1trireguwirewirewandZworshortrealrealr   [a-zA-Z_]\w*:(?!:)\$?[a-zA-Z_]\w*\\(\S+)"#pop/\\([\\abfnrtv"\']|x[a-fA-F0-9]{2,4}|[0-7]{1,3})	[^\\"\n]+\\[^/\n]+/[*](.|\n)*?[*]/z//.*?\n/	(?<=\\)\n\n	[\w:]+\*?rootr   r   r'   c                 C   s8   d}d| v r|d7 }d| v r$|d7 }d| v r4|d7 }|S )z`Verilog code will use one of reg/wire/assign for sure, and that
        is not common elsewhere.r   r   g?r   r-    )textresultr   r   O/var/www/html/django/DPS/env/lib/python3.9/site-packages/pygments/lexers/hdl.pyanalyse_text   s    zVerilogLexer.analyse_textN)%__name__
__module____qualname____doc__namealiases	filenames	mimetypes_wsr	   Preprocr   r   r   EscapeSingle	Multiliner   Charr   FloatHexBinIntegerOctr
   r   Constantr   	Namespacer   r   BuiltinTypeLabeltokensr   r   r   r   r   r      s   

	
N
	
br   c                !   @   s  e Zd ZdZdZddgZddgZdgZdZde	e
ejd	fd
e	e
eje
fde	e
eje
dfde
fde	eje
fdejfdejfdefdedfdejfdejfdejfdejfdejfdejfdejfdefdejfdefeddd ejfd!efd"ejfed#dd efd$e	ej e
ej!fd%e	ej e
ej!fd&e	ej e
ee
ej!fed'dd ej"fed(dd ejfed)dd ej#fd*ej$fd+efd,efg d-ed.fd/ejfd0efde	eje
fd1efgd2ejfd3ejfd4ejd.fd5ejfd6ejfd7e
d.fgd8ejd.fgd9Z%d:S );r   z
    Extends verilog lexer to recognise all SystemVerilog keywords from IEEE
    1800-2009 standard.

    .. versionadded:: 1.5
    systemverilogsvz*.svz*.svhztext/x-systemverilogr   z^(\s*)(`define)r   r%   r&   r'   r   r   r   r   r   r   r   r   r    r!   z4([1-9][_0-9]*)?\s*\'[sS]?[bB]\s*[xXzZ?01][_xXzZ?01]*z6([1-9][_0-9]*)?\s*\'[sS]?[oO]\s*[xXzZ?0-7][_xXzZ?0-7]*z6([1-9][_0-9]*)?\s*\'[sS]?[dD]\s*[xXzZ?0-9][_xXzZ?0-9]*zB([1-9][_0-9]*)?\s*\'[sS]?[hH]\s*[xXzZ?0-9a-fA-F][_xXzZ?0-9a-fA-F]*z
\'[01xXzZ]z[0-9][_0-9]*r"   )Zinsidedistr   r   z[()\[\],.;\'$]r$   )Z	accept_onaliasr(   r)   r*   r+   r,   assertr-   Zassumer.   beforer/   bindZbinsZbinsofr0   r1   r2   r3   r4   r5   r6   cellcheckerZclockingr7   config
constraintcontextr9   ZcoverZ
covergroupZ
coverpointcrossr:   r;   r<   Zdesignr=   r>   r?   r@   rA   rB   Z
endcheckerZendclockingZ	endconfigrC   rD   ZendgroupZendinterfacerE   rF   rG   Z
endprogramZendpropertyZendsequencerH   rI   rJ   rK   Z
eventuallyexpectZexportZexternrM   Zfirst_matchrN   rO   ZforeachrP   rQ   ZforkjoinrR   rS   rT   globalrU   rV   rW   ZiffZifnoneZignore_binsZillegal_binsZimpliesZ
implementsr'   incdirr   rX   rY   rZ   instanceZinterconnectZ	interfaceZ	intersectr\   Zjoin_anyZ	join_noner]   ZletZliblistlibrarylocalr^   r_   matchesr`   Zmodportra   rb   rc   ZnettypenewZnexttimerd   re   Znoshowcancelledrf   rg   rh   nullri   rj   packagerk   rl   rm   rn   ro   priorityprogrampropertyr   rp   rq   rr   rs   Zpulsestyle_ondetectZpulsestyle_oneventpureZrandZrandcZrandcaseZrandsequencert   ru   Z	reject_onrv   rw   Zrestrictrx   ry   rz   r{   r|   r}   Zs_alwaysZs_eventuallyZ
s_nexttimeZs_untilZs_until_withr~   sequenceZshowcancelledr   ZsoftZsolver   r   Zstaticstrongr   r   r   superZsync_accept_onZsync_reject_onr   Ztaggedr   r   Z
throughoutZtimeprecisionZtimeunitr   r   r   r   unionuniqueZunique0untilZ
until_withZuntypeduser   Zvirtualr   Z
wait_orderZweakr   r   r   ZwildcardwithZwithinr   r   z(class)(\s+)([a-zA-Z_]\w*)z(extends)(\s+)([a-zA-Z_]\w*)z,(endclass\b)(?:(\s*)(:)(\s*)([a-zA-Z_]\w*))?)!r   r   chandler8   rL   r   r[   r   r   r   r   r   r   Z	shortrealr   r   r   r   r   r   r   r   r   r   r   r   r   r   r   r   r   r   Zwor)z	`__FILE__z	`__LINE__z`begin_keywordsz`celldefinez`default_nettypez`definez`elsez`elsifz`end_keywordsz`endcelldefinez`endifz`ifdefz`ifndefz`includez`linez`nounconnected_drivez`pragmaz	`resetallz
`timescalez`unconnected_drivez`undefz`undefineall)z$exitz$finishz$stopz	$realtimez$stimez$timez$printtimescalez$timeformatz$bitstorealz$bitstoshortrealz$castz$itorz$realtobitsz$rtoiz$shortrealtobitsz$signedz	$unsignedz$bitsz$isunboundedz	$typenamez$dimensionsz$highz
$incrementz$leftz$lowz$rightz$sizez$unpacked_dimensionsz$acosz$acoshz$asinz$asinhz$atanz$atan2z$atanhz$ceilz$clog2z$cosz$coshz$expz$floorz$hypotz$lnz$log10z$powz$sinz$sinhz$sqrtz$tanz$tanhz
$countbitsz
$countonesz
$isunknownz$onehotz$onehot0z$infoz$errorz$fatalz$warningz$assertcontrolz$assertfailoffz$assertfailonz$assertkillz$assertnonvacuousonz
$assertoffz	$assertonz$assertpassoffz$assertpassonz$assertvacuousoffz$changedz$changed_gclkz$changing_gclkz$falling_gclkz$fellz
$fell_gclkz$future_gclkz$pastz
$past_gclkz$rising_gclkz$rosez
$rose_gclkz$sampledz$stablez$stable_gclkz$steady_gclkz$coverage_controlz$coverage_getz$coverage_get_maxz$coverage_mergez$coverage_savez$get_coveragez$load_coverage_dbz$set_coverage_db_namez$dist_chi_squarez$dist_erlangz$dist_exponentialz$dist_normalz$dist_poissonz$dist_tz$dist_uniformz$randomz$q_addz$q_examz$q_fullz$q_initializez	$q_removez$async$and$arrayz$async$and$planez$async$nand$arrayz$async$nand$planez$async$nor$arrayz$async$nor$planez$async$or$arrayz$async$or$planez$sync$and$arrayz$sync$and$planez$sync$nand$arrayz$sync$nand$planez$sync$nor$arrayz$sync$nor$planez$sync$or$arrayz$sync$or$planez$systemz$displayz	$displaybz	$displayhz	$displayoz$monitorz	$monitorbz	$monitorhz	$monitoroz$monitoroffz
$monitoronz$strobez$strobebz$strobehz$strobeoz$writez$writebz$writehz$writeoz$fclosez	$fdisplayz
$fdisplaybz
$fdisplayhz
$fdisplayoz$feofz$ferrorz$fflushz$fgetcz$fgetsz	$fmonitorz
$fmonitorbz
$fmonitorhz
$fmonitoroz$fopenz$freadz$fscanfz$fseekz$fstrobez	$fstrobebz	$fstrobehz	$fstrobeoz$ftellz$fwritez$fwritebz$fwritehz$fwriteoz$rewindz$sformatz	$sformatfz$sscanfz$swritez$swritebz$swritehz$swriteoz$ungetcz	$readmembz	$readmemhz
$writemembz
$writememhz$test$plusargsz$value$plusargsz$dumpallz	$dumpfilez
$dumpflushz
$dumplimitz$dumpoffz$dumponz
$dumpportsz$dumpportsallz$dumpportsflushz$dumpportslimitz$dumpportsoffz$dumpportsonz	$dumpvarsr   r   r   r   r   r   r   r   r   r   z//.*?$r   r   r   r   r   N)&r   r   r   r   r   r   r   r   r   r   r   r	   r   r   r   r   r   r   r   r   r   r   r   r   r   r   r   r
   r   Wordr   r   DeclarationClassr   r   r   r   r   r   r   r   r      s   )*,	
	MNP  @
	
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B Zdefdeejefdejfd	ejfd
efdejfdefdefdeeeejfdeeeefdeeeejefdeeeejfdeejejfedddejfdeeeejfdeeeejeeeejee	fdeejeeefdeeeedfedededdefgeddejfdefded fged!ddejfged"ddefgd#ej fd$ej fd%ej!fd&ej"fd'ej#fd(ej$fgd)Z%d*S )+r   z:
    For VHDL source code.

    .. versionadded:: 1.5
    vhdlz*.vhdlz*.vhdztext/x-vhdlr   r   z--.*?$z'(U|X|0|1|Z|W|L|H|-)'r"   z
'[a-z_]\w*r#   z"[^\n\\"]*"z(library)(\s+)([a-z_]\w*)z(use)(\s+)(entity)z(use)(\s+)([a-z_][\w.]*\.)(all)z(use)(\s+)([a-z_][\w.]*)z(std|ieee)(\.[a-z_]\w*))ZstdZieeeZworkr   r   z"(entity|component)(\s+)([a-z_]\w*)zN(architecture|configuration)(\s+)([a-z_]\w*)(\s+)(of)(\s+)([a-z_]\w*)(\s+)(is)z ([a-z_]\w*)(:)(\s+)(process|for)z
(end)(\s+)endblocktypeskeywordsnumbersz	[a-z_]\w*;r   )booleanr   	characterZseverity_levelr[   r   Zdelay_lengthZnaturalZpositiver   Z
bit_vectorZfile_open_kindZfile_open_statusZ
std_ulogicZstd_ulogic_vectorZ	std_logicZstd_logic_vectorr   r   )_absaccessafterr   allr,   architecturearrayr   	attributer/   blockbodybufferbusr4   	componentconfigurationZconstantZ
disconnectZdowntor@   r   rA   entityexitfilerN   rR   rS   ZgenericgroupZguardedrW   ZimpureinZinertialrY   islabelr  linkageliteralloopmapmodrb   r  nextre   rf   r  Zofonopenri   Zothersoutr  portZ	postponedZ	procedureprocessr  rangerecordregisterZrejectremrx   ZrolZrorselectZseveritysignalZsharedZslaZsllsraZsrlsubtypeZthento	transportr   Zunitsr  r  variabler   whenr   r  r   r   z\d{1,2}#[0-9a-f_]+#?z\d+z(\d+\.\d*|\.\d+|\d+)E[+-]?\d+zX"[0-9a-f_]+"z
O"[0-7_]+"z	B"[01_]+")r   r  r  r  r  N)&r   r   r   r   r   r   r   r   re	MULTILINE
IGNORECASEflagsr   r   r   r   r	   r   r   r
   r   	Attributer   r   r   r   r  r   r   r   r   r   r   r   r   r   r   r   r   r   r   r   r   u  s   
&	r   )r   rK  Zpygments.lexerr   r   r   r   r   r   Zpygments.tokenr   r	   r
   r   r   r   r   r   r   __all__r   r   r   r   r   r   r   <module>   s   
 ,~ d